1. Field of the Invention
This invention relates to analog-to-digital converters of the type comprising a linear integrator which functions together with clock-pulse timing controls to convert an unknown analog signal into a corresponding digital number.
2. Description of the Prior Art
The above-identified copending application, Ser. No. 380,690 discloses a new converter concept representing a significant advance over the well known prior-art converters which have been in general use now for some time. In that new converter, a linear integrator is operated through two successive cycles to effect the analog-to-digital conversion. In the first of these two cycles, an error signal is derived representing the total error-producing offset voltage present in the system. In the second cycle, the unknown analog signal is converted to a corresponding digital output signal by a unique arrangement which corrects the digital output for the error component previously determined in the first cycle to provide a highly accurate conversion.
To develop the offset error signal during the first (or "pre-conversion") cycle, fixed-voltage reference signals of effectively opposite polarity are successively applied to the integrator so that its output first ramps away from a datum level for a first fixed period of time (as measured by a clock-pulse timing control), and then ramps back to the datum level. The error signal is represented by the time difference (in number of clock pulses) between (1) the time the integrator output returns to the datum level, and (2) the end of a second fixed period of time beyond the first fixed period of time and equal in duration to that time period.
During the subsequent conversion cycle, which commences immediately upon the return of the integrator output to datum level in the pre-conversion cycle, the unknown analog signal is applied to the integrator to make its output ramp away from the datum level during a third period of time, and then the integrator output is ramped back to its datum level by applying to the integrator an opposite-polarity reference signal. The magnitude of the unknown signal then is defined digitally by the time difference (in number of clock pulses) between (1) the time the integrator output returns to the datum level and (2) a reference clock time. The polarity of the unknown signal is indicated by whether the final return to the datum level occurred before or after the reference clock time.
In one embodiment of the invention disclosed in that earlier application, the third time period (i.e. the period of integration of the unknown input signal) was controlled by stopping the integration at a pre-set time period after the end of the second time period; this pre-set time period was made equal in duration to the preceding second time period (which in turn was equal in duration to the first time period). For developing the digital output signal at the completion of the conversion cycle, the reference clock time was set as the end of a pre-fixed time period beyond the third time period, with this pre-fixed time period being equal in duration to the immediately preceding pre-set time period.
In the above-described embodiment, the end of the third time period (i.e. the period during which the unknown signal was integrated) always occurred at a fixed time beyond the start of the pre-conversion cycle, whereas the start time of the third period varied, depending upon the magnitdue of the previously defined offset error signal. Thus the digital error signal was automatically introduced into the conversion cycle by correspondingly altering the amount of integration time to which the unknown signal was subjected, compensating for offset error so as to achieve markedly improved accuracy.
In another embodiment of the invention disclosed in the above-identified copending application, a still further improvement in accuracy was obtained by using the digital error signal to control not only the start time of the integration of the unknown signal, but also to control (1) the ending time of that integration, and (2) the reference clock time used as a base for developing the digital output signal. This more precise arrangement did require somewhat more complex equipment, and the circuitry for effecting the needed time controls introduced some unwanted design characteristics. For example, means had to be provided to store the digital error signal developed during the pre-conversion cycle, and means had to be provided to divide the stored digital error signal by a factor of two prior to using that signal for controlling the conversion operation. The present invention is aimed at achieving the desired high accuracy with a considerably simpler circuit arrangement which does not introduce undesirable design characteristics. The present invention also permits a more rapid conversion operation.